summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/Math.scala
diff options
context:
space:
mode:
authorJack2022-01-12 04:27:19 +0000
committerJack2022-01-12 04:27:19 +0000
commit29df513e348cc809876893f650af8180f0190496 (patch)
tree06daaea954b4e5af7113f06e4bdbb78b33515cb3 /src/test/scala/chiselTests/Math.scala
parent5242ce90659decb9058ee75db56e5c188029fbf9 (diff)
parent747d16311bdf185d2e98e452b14cb5d8ccca004c (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/Math.scala')
-rw-r--r--src/test/scala/chiselTests/Math.scala60
1 files changed, 31 insertions, 29 deletions
diff --git a/src/test/scala/chiselTests/Math.scala b/src/test/scala/chiselTests/Math.scala
index 9091b0b4..42eff6ad 100644
--- a/src/test/scala/chiselTests/Math.scala
+++ b/src/test/scala/chiselTests/Math.scala
@@ -10,41 +10,43 @@ class Math extends ChiselPropSpec {
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
implicit val noShrinkInt = Shrink[Int](_ => Stream.empty)
- property ("unsignedBitLength is computed correctly") {
- forAll(safeUIntWidth) { case (width: Int) =>
- for ( offset <- List(-1, 0, 1)) {
- val n = (1 << width) + offset
- if (n >= 0) {
- val d = unsignedBitLength(n)
- val t = if (n == 0) 0 else if (offset < 0) width else width + 1
- d shouldEqual (t)
+ property("unsignedBitLength is computed correctly") {
+ forAll(safeUIntWidth) {
+ case (width: Int) =>
+ for (offset <- List(-1, 0, 1)) {
+ val n = (1 << width) + offset
+ if (n >= 0) {
+ val d = unsignedBitLength(n)
+ val t = if (n == 0) 0 else if (offset < 0) width else width + 1
+ d shouldEqual (t)
+ }
}
- }
}
}
- property ("signedBitLength is computed correctly") {
- forAll(safeUIntWidth) { case (width: Int) =>
- for ( offset <- List(-1, 0, 1)) {
- for ( mult <- List(-1, +1)) {
- val n = ((1 << (width - 1)) + offset) * mult
- val d = signedBitLength(n)
- val t = n match {
- case -2 => 2
- case -1 => 1
- case 0 => 0
- case 1 => 2
- case 2 => 3
- case _ =>
- if (n > 0) {
- if (offset < 0) width else width + 1
- } else {
- if (offset > 0) width + 1 else width
- }
+ property("signedBitLength is computed correctly") {
+ forAll(safeUIntWidth) {
+ case (width: Int) =>
+ for (offset <- List(-1, 0, 1)) {
+ for (mult <- List(-1, +1)) {
+ val n = ((1 << (width - 1)) + offset) * mult
+ val d = signedBitLength(n)
+ val t = n match {
+ case -2 => 2
+ case -1 => 1
+ case 0 => 0
+ case 1 => 2
+ case 2 => 3
+ case _ =>
+ if (n > 0) {
+ if (offset < 0) width else width + 1
+ } else {
+ if (offset > 0) width + 1 else width
+ }
+ }
+ d shouldEqual (t)
}
- d shouldEqual (t)
}
- }
}
}
}