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authorJack Koenig2017-12-14 15:36:19 -0800
committerGitHub2017-12-14 15:36:19 -0800
commit74de925ab437ef999a92b36630ebc4965992fdbf (patch)
tree6d3c6bc52ec90820703fd8e91e3b7395836d2fee /src/test/scala/chiselTests/InvalidateAPISpec.scala
parentef1400f45404210121f53b38585602a8c7c2560e (diff)
Fix a few compiler warnings (#738)
Make InvalidateAPI emit to a test directory Add *.swp and test_run_dir to .gitignore
Diffstat (limited to 'src/test/scala/chiselTests/InvalidateAPISpec.scala')
-rw-r--r--src/test/scala/chiselTests/InvalidateAPISpec.scala6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala
index 87a69fe0..c0a643cc 100644
--- a/src/test/scala/chiselTests/InvalidateAPISpec.scala
+++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala
@@ -6,13 +6,15 @@ import chisel3._
import chisel3.core.BiConnect.BiConnectException
import chisel3.util.Counter
import firrtl.passes.CheckInitialization.RefNotInitializedException
+import firrtl.util.BackendCompilationUtilities
import org.scalatest._
-class InvalidateAPISpec extends ChiselPropSpec with Matchers {
+class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompilationUtilities {
def myGenerateFirrtl(t: => Module): String = Driver.emit(() => t)
def compileFirrtl(t: => Module): Unit = {
- Driver.execute(Array[String]("--compiler", "verilog"), () => t)
+ val testDir = createTestDirectory(this.getClass.getSimpleName)
+ Driver.execute(Array[String]("-td", testDir.getAbsolutePath, "--compiler", "verilog"), () => t)
}
class TrivialInterface extends Bundle {
val in = Input(Bool())