diff options
| author | Schuyler Eldridge | 2020-06-16 11:59:15 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-06-22 20:00:10 -0400 |
| commit | 6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a (patch) | |
| tree | 482481bcfe93ea5dfcece80772ce1957fb68c74c /src/test/scala/chiselTests/InvalidateAPISpec.scala | |
| parent | cc4fa583690292d690804144fe92427f0c9f5fdf (diff) | |
Use ChiselStage in Tests
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:
- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/InvalidateAPISpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/InvalidateAPISpec.scala | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 574fc88b..f0841ef0 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -3,18 +3,21 @@ package chiselTests import chisel3._ +import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} import chisel3.util.Counter import firrtl.passes.CheckInitialization.RefNotInitializedException import firrtl.util.BackendCompilationUtilities import org.scalatest._ import org.scalatest.matchers.should.Matchers -class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompilationUtilities { +class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompilationUtilities with Utils { - def myGenerateFirrtl(t: => Module): String = Driver.emit(() => t) + def myGenerateFirrtl(t: => Module): String = (new ChiselStage).emitChirrtl(t) def compileFirrtl(t: => Module): Unit = { val testDir = createTestDirectory(this.getClass.getSimpleName) - Driver.execute(Array[String]("-td", testDir.getAbsolutePath, "--compiler", "verilog"), () => t) + + (new ChiselStage).execute(Array[String]("-td", testDir.getAbsolutePath, "--compiler", "verilog"), + Seq(ChiselGeneratorAnnotation(() => t))) } class TrivialInterface extends Bundle { val in = Input(Bool()) @@ -99,7 +102,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila DontCare := io.in } val exception = intercept[ChiselException] { - elaborate(new ModuleWithDontCareSink) + extractCause[ChiselException] { + ChiselStage.elaborate(new ModuleWithDontCareSink) + } } exception.getMessage should include("DontCare cannot be a connection sink (LHS)") } @@ -111,7 +116,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila DontCare <> io.in } val exception = intercept[BiConnectException] { - elaborate(new ModuleWithDontCareSink) + extractCause[BiConnectException] { + ChiselStage.elaborate(new ModuleWithDontCareSink) + } } exception.getMessage should include("DontCare cannot be a connection sink (LHS)") } |
