diff options
| author | Albert Magyar | 2020-07-21 17:40:16 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-21 17:40:16 -0700 |
| commit | 473a13877c60ba9fb13de47542a8397412c2b967 (patch) | |
| tree | 159cec6aa6ece2e87ceffbdc56a553fe71d0726b /src/test/scala/chiselTests/InvalidateAPISpec.scala | |
| parent | 4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff) | |
| parent | e5568f55a6a149adfd19ad04b264a69078288f86 (diff) | |
Merge pull request #1519 from freechipsproject/no-scalastyle
Remove scalastyle configurations
Diffstat (limited to 'src/test/scala/chiselTests/InvalidateAPISpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/InvalidateAPISpec.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index f0841ef0..5890310e 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -24,7 +24,6 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val out = Output(Bool()) } - // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { @@ -215,5 +214,4 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } - // scalastyle:on line.size.limit } |
