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| author | Jack | 2022-04-26 02:53:08 +0000 |
|---|---|---|
| committer | Jack | 2022-04-26 02:53:08 +0000 |
| commit | 3a6cc75d72cbf890bbd45a002c31d16abfc6896d (patch) | |
| tree | 298a39cbdbcd7e89953d75dbd840884f29ff7699 /src/test/scala/chiselTests/InvalidateAPISpec.scala | |
| parent | be1ac06bf20c6c3d84c8ce5b0a50e2980e546e7e (diff) | |
| parent | d5a964f6e7beea1f38f9623224fc65e2397e1fe7 (diff) | |
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/InvalidateAPISpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/InvalidateAPISpec.scala | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 2c51e5d2..dbd353a0 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -228,4 +228,12 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } + + property("a clock should be able to be connected to a DontCare") { + class ClockConnectedToDontCare extends Module { + val foo = IO(Output(Clock())) + foo := DontCare + } + myGenerateFirrtl(new ClockConnectedToDontCare) should include("foo is invalid") + } } |
