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authorJack2021-12-18 08:27:38 +0000
committerJack2021-12-18 08:27:38 +0000
commitdd9ad534771247ac16eaa47eb9794102736b5102 (patch)
treed4566d317cb8526b79017de1e438aea8217dd1d4 /src/test/scala/chiselTests/IntervalSpec.scala
parent440edc4436fb3a8a4175ae425a0d31c4997ee60f (diff)
parentf50f74f583fba7b98e550c440df091e559ce32b8 (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/IntervalSpec.scala')
-rw-r--r--src/test/scala/chiselTests/IntervalSpec.scala9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala
index abc619e5..c223260d 100644
--- a/src/test/scala/chiselTests/IntervalSpec.scala
+++ b/src/test/scala/chiselTests/IntervalSpec.scala
@@ -15,7 +15,7 @@ import firrtl.passes.CheckTypes.InvalidConnect
import firrtl.passes.CheckWidths.{DisjointSqueeze, InvalidRange}
import firrtl.passes.{PassExceptions, WrapWithRemainder}
import firrtl.stage.{CompilerAnnotation, FirrtlCircuitAnnotation}
-import firrtl.{FIRRTLException, HighFirrtlCompiler, LowFirrtlCompiler, MiddleFirrtlCompiler, MinimumVerilogCompiler, NoneCompiler, SystemVerilogCompiler, VerilogCompiler}
+import firrtl.{HighFirrtlCompiler, LowFirrtlCompiler, MiddleFirrtlCompiler, MinimumVerilogCompiler, NoneCompiler, SystemVerilogCompiler, VerilogCompiler}
import org.scalatest.freespec.AnyFreeSpec
import org.scalatest.matchers.should.Matchers
@@ -406,6 +406,13 @@ class IntervalChainedSubTester extends BasicTester {
assert(intervalResult1 === 5.I)
assert(intervalResult2 === 5.I)
+ val negativeInterval = (-3.5).I(4.BP)
+ val positiveInterval = 3.5.I(4.BP)
+
+ assert(negativeInterval =/= positiveInterval)
+ assert(-negativeInterval === positiveInterval)
+ assert(negativeInterval === -positiveInterval)
+
stop()
}