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authorSchuyler Eldridge2019-05-09 13:55:53 -0400
committerGitHub2019-05-09 13:55:53 -0400
commita9bf10cc40a5acf0f4bfb43744f9e12e8e1a0e25 (patch)
tree5ce84e585188bf1a934f6b404dc26e1d4175b83d /src/test/scala/chiselTests/InstanceNameSpec.scala
parent0479e47e8294c5b242bbf36d19b1f5a06c32e6c1 (diff)
parentaaee64deb9c4990d0e38043a2b6a4ce747bb6935 (diff)
Merge pull request #1088 from freechipsproject/lfsr
- Add chisel3.util.random package with Galois and Fibonacci LFSRs - Add maximal period LFSR generation and maximal period taps - Deprecate chisel3.util.LFSR16 in favor of chisel3.util.random.LFSR(16)
Diffstat (limited to 'src/test/scala/chiselTests/InstanceNameSpec.scala')
-rw-r--r--src/test/scala/chiselTests/InstanceNameSpec.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/InstanceNameSpec.scala b/src/test/scala/chiselTests/InstanceNameSpec.scala
index 30dc46ba..7bb91b94 100644
--- a/src/test/scala/chiselTests/InstanceNameSpec.scala
+++ b/src/test/scala/chiselTests/InstanceNameSpec.scala
@@ -3,6 +3,7 @@
package chiselTests
import chisel3._
+import chisel3.util.Queue
import chisel3.experimental.{DataMirror, FixedPoint}
import chisel3.testers.BasicTester
@@ -17,7 +18,7 @@ class InstanceNameModule extends Module {
val foo = UInt(8.W)
}
- val q = Module(new util.Queue(UInt(32.W), 4))
+ val q = Module(new Queue(UInt(32.W), 4))
io.bar := io.foo + x
}