diff options
| author | Schuyler Eldridge | 2018-08-21 14:32:13 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-08-23 14:05:20 -0400 |
| commit | 87551bf5f56d52198efaabdeb69dcd15fb230954 (patch) | |
| tree | 9e7464dc06123b102045ed04136666efd0308ae8 /src/test/scala/chiselTests/InlineSpec.scala | |
| parent | ee0f27c50f8d029721e69c0e7a7bd47b9a4c1d02 (diff) | |
Add FlattenInstance API
This adds a new trait, FlattenInstance, to chisel3.util.experimental. When
mixed into a module or a specific instance this trait will "flatten",
i.e., "inline that module and all of its submodules".
This includes testing (additions to InlineSpec) and ScalaDoc
documentation.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/InlineSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/InlineSpec.scala | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala index 4482d9ec..a2aabdb3 100644 --- a/src/test/scala/chiselTests/InlineSpec.scala +++ b/src/test/scala/chiselTests/InlineSpec.scala @@ -3,11 +3,12 @@ package chiselTests import chisel3._ -import chisel3.util.experimental.InlineInstance +import chisel3.util.experimental.{InlineInstance, FlattenInstance} import chisel3.internal.firrtl.Circuit import firrtl.FirrtlExecutionSuccess import firrtl.passes.InlineAnnotation import firrtl.annotations.Annotation +import firrtl.transforms.FlattenAnnotation import firrtl.analyses.InstanceGraph import firrtl.{ir => fir} import firrtl.WDefInstance @@ -54,4 +55,23 @@ class InlineSpec extends FreeSpec with ChiselRunners with Matchers { } } } + + "Module Flattening" - { + class Top extends Module with Internals { + val x = Module(new Qux with FlattenInstance) + x.io.a := io.a + } + "should compile to low FIRRTL" - { + Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new Top) match { + case ChiselExecutionSuccess(Some(chiselCircuit), chirrtl, Some(firrtlResult: FirrtlExecutionSuccess)) => + "emitting ONE FlattenAnnotation at the CHIRRTL level" in { + chiselCircuit.annotations.map(_.toFirrtl).collect{ case a: FlattenAnnotation => a }.size should be (1) + } + "low FIRRTL should contain instance x only" in { + val instances = collectInstances(firrtlResult.circuitState.circuit, Some("Top")).toSet + Set("Top", "Top.x") should be (instances) + } + } + } + } } |
