Use ChiselStage in Tests

This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:

- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
  methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 37 insertions, 20 deletions

diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala
index a7d95fad..2d9bd792 100644
--- a/src/test/scala/chiselTests/InlineSpec.scala
+++ b/src/test/scala/chiselTests/InlineSpec.scala
@@ -3,9 +3,11 @@
 package chiselTests
 
 import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util.experimental.{InlineInstance, FlattenInstance}
 import firrtl.FirrtlExecutionSuccess
 import firrtl.passes.InlineAnnotation
+import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage}
 import firrtl.transforms.FlattenAnnotation
 import firrtl.analyses.InstanceGraph
 import firrtl.{ir => fir}
@@ -32,6 +34,9 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
     .fullHierarchy.values.flatten.toSeq
     .map( v => (top.getOrElse(v.head.name) +: v.tail.map(_.name)).mkString(".") )
 
+  val chiselStage = new ChiselStage
+  val firrtlStage = new FirrtlStage
+
   "Module Inlining" - {
     class Top extends Module with Internals {
       val x = Module(new Foo)
@@ -40,16 +45,22 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
       Seq(x, y, z).map(_.io.a := io.a)
     }
     "should compile to low FIRRTL" - {
-      Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new Top) match {
-        case ChiselExecutionSuccess(Some(chiselCircuit), _, Some(firrtlResult: FirrtlExecutionSuccess)) =>
-          "emitting TWO InlineAnnotation at the CHIRRTL level" in {
-            chiselCircuit.annotations.map(_.toFirrtl).collect{ case a: InlineAnnotation => a }.size should be (2)
-          }
-          "low FIRRTL should contain only instance z" in {
-            val instances = collectInstances(firrtlResult.circuitState.circuit, Some("Top")).toSet
-            Set("Top", "Top.x_sub", "Top.y_sub", "Top.z", "Top.z.sub") should be (instances)
-          }
-      }
+      val chiselAnnotations =
+        chiselStage
+          .execute(Array("--no-run-firrtl", "--target-dir", "test_run_dir"),
+                   Seq(ChiselGeneratorAnnotation(() => new Top)))
+
+      chiselAnnotations.collect{ case a: InlineAnnotation => a } should have length (2)
+
+      val instanceNames =
+        firrtlStage
+          .execute(Array("-X", "low"), chiselAnnotations)
+          .collectFirst {
+            case FirrtlCircuitAnnotation(circuit) => circuit
+          }.map(collectInstances(_, Some("Top")))
+          .getOrElse(fail)
+
+      instanceNames should contain theSameElementsAs Set("Top", "Top.x_sub", "Top.y_sub", "Top.z", "Top.z.sub")
     }
   }
 
@@ -59,16 +70,22 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
       x.io.a := io.a
     }
     "should compile to low FIRRTL" - {
-      Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new Top) match {
-        case ChiselExecutionSuccess(Some(chiselCircuit), chirrtl, Some(firrtlResult: FirrtlExecutionSuccess)) =>
-          "emitting ONE FlattenAnnotation at the CHIRRTL level" in {
-            chiselCircuit.annotations.map(_.toFirrtl).collect{ case a: FlattenAnnotation => a }.size should be (1)
-          }
-          "low FIRRTL should contain instance x only" in {
-            val instances = collectInstances(firrtlResult.circuitState.circuit, Some("Top")).toSet
-            Set("Top", "Top.x") should be (instances)
-          }
-      }
+      val chiselAnnotations =
+        chiselStage
+          .execute(Array("-X", "low", "--target-dir", "test_run_dir"),
+                   Seq(ChiselGeneratorAnnotation(() => new Top)))
+
+      chiselAnnotations.collect{ case a: FlattenAnnotation => a} should have length(1)
+
+      val instanceNames =
+        firrtlStage
+          .execute(Array("-X", "low"), chiselAnnotations)
+          .collectFirst {
+            case FirrtlCircuitAnnotation(circuit) => circuit
+          }.map(collectInstances(_, Some("Top")))
+          .getOrElse(fail)
+
+      instanceNames should contain theSameElementsAs Set("Top", "Top.x")
     }
   }
 }