Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 19 insertions, 13 deletions

diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala
index 59a1e984..09a92e45 100644
--- a/src/test/scala/chiselTests/InlineSpec.scala
+++ b/src/test/scala/chiselTests/InlineSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
-import chisel3.util.experimental.{InlineInstance, FlattenInstance}
+import chisel3.util.experimental.{FlattenInstance, InlineInstance}
 import firrtl.passes.InlineAnnotation
 import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage}
 import firrtl.transforms.FlattenAnnotation
@@ -16,7 +16,7 @@ import org.scalatest.matchers.should.Matchers
 class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
 
   trait Internals { this: Module =>
-    val io = IO(new Bundle{ val a = Input(Bool()) })
+    val io = IO(new Bundle { val a = Input(Bool()) })
   }
   class Sub extends Module with Internals
   trait HasSub { this: Module with Internals =>
@@ -29,9 +29,9 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
   class Baz extends Module with Internals with HasSub
   class Qux extends Module with Internals with HasSub
 
-  def collectInstances(c: fir.Circuit, top: Option[String] = None): Seq[String] = new InstanceGraph(c)
-    .fullHierarchy.values.flatten.toSeq
-    .map( v => (top.getOrElse(v.head.name) +: v.tail.map(_.name)).mkString(".") )
+  def collectInstances(c: fir.Circuit, top: Option[String] = None): Seq[String] =
+    new InstanceGraph(c).fullHierarchy.values.flatten.toSeq
+      .map(v => (top.getOrElse(v.head.name) +: v.tail.map(_.name)).mkString("."))
 
   val chiselStage = new ChiselStage
   val firrtlStage = new FirrtlStage
@@ -46,17 +46,20 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
     "should compile to low FIRRTL" - {
       val chiselAnnotations =
         chiselStage
-          .execute(Array("--no-run-firrtl", "--target-dir", "test_run_dir"),
-                   Seq(ChiselGeneratorAnnotation(() => new Top)))
+          .execute(
+            Array("--no-run-firrtl", "--target-dir", "test_run_dir"),
+            Seq(ChiselGeneratorAnnotation(() => new Top))
+          )
 
-      chiselAnnotations.collect{ case a: InlineAnnotation => a } should have length (2)
+      (chiselAnnotations.collect { case a: InlineAnnotation => a } should have).length(2)
 
       val instanceNames =
         firrtlStage
           .execute(Array("-X", "low"), chiselAnnotations)
           .collectFirst {
             case FirrtlCircuitAnnotation(circuit) => circuit
-          }.map(collectInstances(_, Some("Top")))
+          }
+          .map(collectInstances(_, Some("Top")))
           .getOrElse(fail)
 
       instanceNames should contain theSameElementsAs Set("Top", "Top.x_sub", "Top.y_sub", "Top.z", "Top.z.sub")
@@ -71,17 +74,20 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers {
     "should compile to low FIRRTL" - {
       val chiselAnnotations =
         chiselStage
-          .execute(Array("--no-run-firrtl", "--target-dir", "test_run_dir"),
-                   Seq(ChiselGeneratorAnnotation(() => new Top)))
+          .execute(
+            Array("--no-run-firrtl", "--target-dir", "test_run_dir"),
+            Seq(ChiselGeneratorAnnotation(() => new Top))
+          )
 
-      chiselAnnotations.collect{ case a: FlattenAnnotation => a} should have length(1)
+      (chiselAnnotations.collect { case a: FlattenAnnotation => a } should have).length(1)
 
       val instanceNames =
         firrtlStage
           .execute(Array("-X", "low"), chiselAnnotations)
           .collectFirst {
             case FirrtlCircuitAnnotation(circuit) => circuit
-          }.map(collectInstances(_, Some("Top")))
+          }
+          .map(collectInstances(_, Some("Top")))
           .getOrElse(fail)
 
       instanceNames should contain theSameElementsAs Set("Top", "Top.x")