diff options
| author | Jim Lawson | 2016-12-02 12:51:03 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-02 12:51:03 -0800 |
| commit | d3ec37edd39799e8cf039e5caed915c00dff7eeb (patch) | |
| tree | 03329ddc11ca15b9d6c7f832354a9cba20c87843 /src/test/scala/chiselTests/IOCompatibility.scala | |
| parent | 1b53d893816d349f5ea18fa0ed13325b9f1b6917 (diff) | |
| parent | eba224e524b249207b47a3b378458c61c9b66e2c (diff) | |
Merge branch 'master' into exceptionfix
Diffstat (limited to 'src/test/scala/chiselTests/IOCompatibility.scala')
| -rw-r--r-- | src/test/scala/chiselTests/IOCompatibility.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index 552fe776..521e895d 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -7,19 +7,19 @@ import chisel3.core.Binding.BindingException import org.scalatest._ class IOCSimpleIO extends Bundle { - val in = Input(UInt(width=32)) - val out = Output(UInt(width=32)) + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) } class IOCPlusOne extends Module { val io = IO(new IOCSimpleIO) - io.out := io.in + UInt(1) + io.out := io.in + 1.U } class IOCModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Vec(n, Input(UInt(width=32))) - val outs = Vec(n, Output(UInt(width=32))) + val ins = Vec(n, Input(UInt(32.W))) + val outs = Vec(n, Output(UInt(32.W))) }) val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } for (i <- 0 until n) { |
