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authorRichard Lin2017-08-17 17:24:02 -0700
committerJack Koenig2017-08-17 17:24:02 -0700
commit6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 (patch)
tree0ff452193d515adc32ecccacb2b58daa9a1d95cb /src/test/scala/chiselTests/IOCompatibility.scala
parent802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 (diff)
More of the bindings refactor (#635)
Rest of the binding refactor
Diffstat (limited to 'src/test/scala/chiselTests/IOCompatibility.scala')
-rw-r--r--src/test/scala/chiselTests/IOCompatibility.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 521e895d..28058963 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -21,7 +21,7 @@ class IOCModuleVec(val n: Int) extends Module {
val ins = Vec(n, Input(UInt(32.W)))
val outs = Vec(n, Output(UInt(32.W)))
})
- val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+ val pluses = VecInit(Seq.fill(n){ Module(new IOCPlusOne).io })
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
io.outs(i) := pluses(i).out