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authorducky2016-11-17 13:01:03 -0800
committerducky2016-11-21 13:31:12 -0800
commit54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch)
tree7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/IOCompatibility.scala
parentcd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff)
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/IOCompatibility.scala')
-rw-r--r--src/test/scala/chiselTests/IOCompatibility.scala10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 552fe776..521e895d 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -7,19 +7,19 @@ import chisel3.core.Binding.BindingException
import org.scalatest._
class IOCSimpleIO extends Bundle {
- val in = Input(UInt(width=32))
- val out = Output(UInt(width=32))
+ val in = Input(UInt(32.W))
+ val out = Output(UInt(32.W))
}
class IOCPlusOne extends Module {
val io = IO(new IOCSimpleIO)
- io.out := io.in + UInt(1)
+ io.out := io.in + 1.U
}
class IOCModuleVec(val n: Int) extends Module {
val io = IO(new Bundle {
- val ins = Vec(n, Input(UInt(width=32)))
- val outs = Vec(n, Output(UInt(width=32)))
+ val ins = Vec(n, Input(UInt(32.W)))
+ val outs = Vec(n, Output(UInt(32.W)))
})
val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
for (i <- 0 until n) {