Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 5 insertions, 6 deletions

diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 61789ffa..3e01a7a5 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -8,7 +8,7 @@ import org.scalatest._
 import org.scalatest.matchers.should.Matchers
 
 class IOCSimpleIO extends Bundle {
-  val in  = Input(UInt(32.W))
+  val in = Input(UInt(32.W))
   val out = Output(UInt(32.W))
 }
 
@@ -19,13 +19,13 @@ class IOCPlusOne extends Module {
 
 class IOCModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Vec(n, Input(UInt(32.W)))
+    val ins = Vec(n, Input(UInt(32.W)))
     val outs = Vec(n, Output(UInt(32.W)))
   })
-  val pluses = VecInit(Seq.fill(n){ Module(new IOCPlusOne).io })
+  val pluses = VecInit(Seq.fill(n) { Module(new IOCPlusOne).io })
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
-    io.outs(i)   := pluses(i).out
+    io.outs(i) := pluses(i).out
   }
 }
 
@@ -46,14 +46,13 @@ class IOCompatibilitySpec extends ChiselPropSpec with Matchers with Utils {
     ChiselStage.elaborate { new IOCModuleWire }
   }
 
-
   class IOUnwrapped extends Module {
     val io = new IOCSimpleIO
     io.out := io.in
   }
 
   property("Unwrapped IO should generate an exception") {
-    a [BindingException] should be thrownBy extractCause[BindingException] {
+    a[BindingException] should be thrownBy extractCause[BindingException] {
       ChiselStage.elaborate(new IOUnwrapped)
     }
   }