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authorJim Lawson2016-07-20 17:08:55 -0700
committerJim Lawson2016-07-20 17:08:55 -0700
commit1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 (patch)
tree1cea032150aae31fdf7cb995b26724be4b0ceb38 /src/test/scala/chiselTests/GCD.scala
parent2dce378deda1cc33833eb378c89a1c5415817bae (diff)
More literal/width rangling.
Diffstat (limited to 'src/test/scala/chiselTests/GCD.scala')
-rw-r--r--src/test/scala/chiselTests/GCD.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d0d945b7..5e4c897a 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -15,8 +15,8 @@ class GCD extends Module {
val z = Output(UInt.width(32))
val v = Output(Bool())
})
- val x = Reg(UInt(width = 32))
- val y = Reg(UInt(width = 32))
+ val x = Reg(UInt.width( 32))
+ val y = Reg(UInt.width( 32))
when (x > y) { x := x -% y }
.otherwise { y := y -% x }
when (io.e) { x := io.a; y := io.b }