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authorJack Koenig2021-09-17 21:01:26 -0700
committerJack Koenig2021-09-17 21:01:26 -0700
commit5c8c19345e6711279594cf1f9ddab33623c8eba7 (patch)
treed9d6ced3934aa4a8be3dec19ddcefe50a7a93d5a /src/test/scala/chiselTests/ExtModuleImpl.scala
parente63b9667d89768e0ec6dc8a9153335cb48a213a7 (diff)
parent958904cb2f2f65d02b2ab3ec6d9ec2e06d04e482 (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/ExtModuleImpl.scala')
-rw-r--r--src/test/scala/chiselTests/ExtModuleImpl.scala23
1 files changed, 19 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/ExtModuleImpl.scala b/src/test/scala/chiselTests/ExtModuleImpl.scala
index f71a1335..c6cd4a9f 100644
--- a/src/test/scala/chiselTests/ExtModuleImpl.scala
+++ b/src/test/scala/chiselTests/ExtModuleImpl.scala
@@ -8,11 +8,11 @@ import chisel3._
import chisel3.experimental.ExtModule
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import chisel3.util.{HasExtModuleInline, HasExtModulePath, HasExtModuleResource}
-import firrtl.FirrtlExecutionSuccess
import firrtl.options.TargetDirAnnotation
import firrtl.stage.FirrtlCircuitAnnotation
-import org.scalacheck.Test.Failed
-import org.scalatest.{FreeSpec, Matchers, Succeeded}
+import firrtl.transforms.BlackBoxNotFoundException
+import org.scalatest.freespec.AnyFreeSpec
+import org.scalatest.matchers.should.Matchers
//scalastyle:off magic.number
@@ -92,7 +92,16 @@ class UsesExtModuleMinusViaPath extends Module {
io.out := mod0.io.out
}
-class ExtModuleImplSpec extends FreeSpec with Matchers {
+class ExtModuleResourceNotFound extends HasExtModuleResource {
+ val io = IO(new Bundle{})
+ addResource("/missing.resource")
+}
+
+class UsesMissingExtModuleResource extends RawModule {
+ val foo = Module(new ExtModuleResourceNotFound)
+}
+
+class ExtModuleImplSpec extends AnyFreeSpec with Matchers {
"ExtModule can have verilator source implementation" - {
"Implementations can be contained in-line" in {
@@ -137,5 +146,11 @@ class ExtModuleImplSpec extends FreeSpec with Matchers {
verilogOutput.exists() should be(true)
verilogOutput.delete()
}
+
+ "Resource files that do not exist produce Chisel errors" in {
+ assertThrows[BlackBoxNotFoundException]{
+ ChiselStage.emitChirrtl(new UsesMissingExtModuleResource)
+ }
+ }
}
}