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authorducky2016-11-17 13:01:03 -0800
committerducky2016-11-21 13:31:12 -0800
commit54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch)
tree7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/EnableShiftRegister.scala
parentcd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff)
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
-rw-r--r--src/test/scala/chiselTests/EnableShiftRegister.scala12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f3e0dd1..6dc4aac6 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,14 +6,14 @@ import chisel3.testers.BasicTester
class EnableShiftRegister extends Module {
val io = IO(new Bundle {
- val in = Input(UInt.width(4))
+ val in = Input(UInt(4.W))
val shift = Input(Bool())
- val out = Output(UInt.width(4))
+ val out = Output(UInt(4.W))
})
- val r0 = Reg(init = UInt(0, 4))
- val r1 = Reg(init = UInt(0, 4))
- val r2 = Reg(init = UInt(0, 4))
- val r3 = Reg(init = UInt(0, 4))
+ val r0 = Reg(init = 0.U(4.W))
+ val r1 = Reg(init = 0.U(4.W))
+ val r2 = Reg(init = 0.U(4.W))
+ val r3 = Reg(init = 0.U(4.W))
when(io.shift) {
r0 := io.in
r1 := r0