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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/EnableShiftRegister.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
-rw-r--r--src/test/scala/chiselTests/EnableShiftRegister.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 34dcecb0..4d407169 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,9 +6,9 @@ import chisel3.stage.ChiselStage
class EnableShiftRegister extends Module {
val io = IO(new Bundle {
- val in = Input(UInt(4.W))
+ val in = Input(UInt(4.W))
val shift = Input(Bool())
- val out = Output(UInt(4.W))
+ val out = Output(UInt(4.W))
})
val r0 = RegInit(0.U(4.W))
val r1 = RegInit(0.U(4.W))
@@ -41,7 +41,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
expect(c.io.out, reg(3))
}
}
-*/
+ */
class EnableShiftRegisterSpec extends ChiselPropSpec {
@@ -49,5 +49,5 @@ class EnableShiftRegisterSpec extends ChiselPropSpec {
ChiselStage.elaborate { new EnableShiftRegister }
}
- ignore("EnableShiftRegisterTester should return the correct result") { }
+ ignore("EnableShiftRegisterTester should return the correct result") {}
}