diff options
| author | Schuyler Eldridge | 2020-08-26 18:51:09 -0400 |
|---|---|---|
| committer | GitHub | 2020-08-26 15:51:09 -0700 |
| commit | b0389cc905eb19103cc4bc55e9ec9666c9939dca (patch) | |
| tree | 15ae842ca3f1b936e1c89cbf85ea98049d43632b /src/test/scala/chiselTests/Direction.scala | |
| parent | ca80db225c8bf0248068fa8c2531ca440f96ec4a (diff) | |
Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselStage$ helpers (#1566)
* Add ChiselPhase
* Use ChiselPhase in ChiselStage, remove targets
Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.
* Stop writing to files in ChiselStage$ methods
Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.
* Test that ChiselStage$ methods write no files
Modify existing ChiselStage object method tests to check that no files
are written.
* Expand ChiselStage$ API with more helpers
This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.
Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.
* Add tests of new ChiselStage$ helper methods
* Use ChiselStage object in tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/chiselTests/Direction.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Direction.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 52d7a20b..14977804 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -240,7 +240,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils { assert(DataMirror.directionOf(flippedVecFlipped(index).b) == Direction.Output) } - val emitted: String = (new ChiselStage).emitChirrtl(new MyModule) + val emitted: String = ChiselStage.emitChirrtl(new MyModule) val firrtl: String = ChiselStage.convert(new MyModule).serialize // Check that emitted directions are correct. @@ -307,7 +307,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils { assert(DataMirror.directionOf(vecOutputFlipped(index).b) == Direction.Output) } - val emitted: String = (new ChiselStage).emitChirrtl(new MyModule) + val emitted: String = ChiselStage.emitChirrtl(new MyModule) val firrtl: String = ChiselStage.convert(new MyModule).serialize // Check that emitted directions are correct. |