Literals set their ref so they no longer get named (#826)

Fixes #763
Add tests for #763 and #472

This has a few implications
* Constructing a literal no longer increments _T_ suffixes
* Internally, wrapping a literal Bits in Node(...) will work
* Literal Bools work in withReset/withClockAndReset

1 files changed, 29 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/DedupSpec.scala b/src/test/scala/chiselTests/DedupSpec.scala
index b8fe075e..1f2caf7b 100644
--- a/src/test/scala/chiselTests/DedupSpec.scala
+++ b/src/test/scala/chiselTests/DedupSpec.scala
@@ -41,6 +41,31 @@ class NestedDedup extends Module {
   io.out <> inst1.io.out
 }
 
+object DedupConsts {
+  val foo = 3.U
+}
+
+class SharedConstantValDedup extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+  io.out := io.in + DedupConsts.foo
+}
+
+class SharedConstantValDedupTop extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+  val inst0 = Module(new SharedConstantValDedup)
+  val inst1 = Module(new SharedConstantValDedup)
+  inst0.io.in := io.in
+  inst1.io.in := io.in
+  io.out := inst0.io.out + inst1.io.out
+}
+
+
 class DedupSpec extends ChiselFlatSpec {
   private val ModuleRegex = """\s*module\s+(\w+)\b.*""".r
   def countModules(verilog: String): Int =
@@ -53,5 +78,9 @@ class DedupSpec extends ChiselFlatSpec {
   it should "properly dedup modules with deduped submodules" in {
     assert(countModules(compile { new NestedDedup }) === 3)
   }
+
+  it should "dedup modules that share a literal" in {
+    assert(countModules(compile { new SharedConstantValDedupTop  }) === 2)
+  }
 }