Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests

Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk

1 files changed, 4 insertions, 4 deletions

diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 5586561b..b50a80c0 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -11,10 +11,10 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
-  val io = new Bundle {
-    val inst  = UInt(INPUT, 32)
-    val matched = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val inst  = Input(UInt.width(32))
+    val matched = Output(Bool())
+  })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
 }