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authorJack2021-12-18 08:27:38 +0000
committerJack2021-12-18 08:27:38 +0000
commitdd9ad534771247ac16eaa47eb9794102736b5102 (patch)
treed4566d317cb8526b79017de1e438aea8217dd1d4 /src/test/scala/chiselTests/ConnectSpec.scala
parent440edc4436fb3a8a4175ae425a0d31c4997ee60f (diff)
parentf50f74f583fba7b98e550c440df091e559ce32b8 (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/ConnectSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ConnectSpec.scala35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
index 367864e6..f9ef5946 100644
--- a/src/test/scala/chiselTests/ConnectSpec.scala
+++ b/src/test/scala/chiselTests/ConnectSpec.scala
@@ -2,6 +2,8 @@
package chiselTests
+import org.scalatest._
+
import chisel3._
import chisel3.experimental.{Analog, FixedPoint}
import chisel3.stage.ChiselStage
@@ -126,4 +128,37 @@ class ConnectSpec extends ChiselPropSpec with Utils {
property("Pipe internal connections should succeed") {
ChiselStage.elaborate( new PipeInternalWires)
}
+
+ property("Connect error messages should have meaningful information") {
+ class InnerExample extends Module {
+ val myReg = RegInit(0.U(8.W))
+ }
+
+ class OuterAssignExample extends Module {
+ val inner = Module(new InnerExample())
+ inner.myReg := false.B // ERROR
+ }
+
+ val assignError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterAssignExample}}
+ val expectedAssignError = """.*@: myReg in InnerExample cannot be written from module OuterAssignExample."""
+ assignError.getMessage should fullyMatch regex expectedAssignError
+
+ class OuterReadExample extends Module {
+ val myReg = RegInit(0.U(8.W))
+ val inner = Module(new InnerExample())
+ myReg := inner.myReg // ERROR
+ }
+
+ val readError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterReadExample }}
+ val expectedReadError = """.*@: myReg in InnerExample cannot be read from module OuterReadExample."""
+ readError.getMessage should fullyMatch regex expectedReadError
+
+ val typeMismatchError = the [ChiselException] thrownBy {ChiselStage.elaborate { new RawModule {
+ val myUInt = Wire(UInt(4.W))
+ val mySInt = Wire(SInt(4.W))
+ myUInt := mySInt
+ }}}
+ val expectedTypeMismatchError = """.*@: Sink \(UInt<4>\) and Source \(SInt<4>\) have different types."""
+ typeMismatchError.getMessage should fullyMatch regex expectedTypeMismatchError
+ }
}