diff options
| author | ducky | 2015-12-11 14:25:42 -0800 |
|---|---|---|
| committer | ducky | 2015-12-11 17:16:30 -0800 |
| commit | dbd072172f6312893e1922e48ed768ae0fab9a89 (patch) | |
| tree | c3a0f10dd286ae2bba50c31b987ab39c45189898 /src/test/scala/chiselTests/ComplexAssign.scala | |
| parent | bffc67c2bbeb107d2ff9903aa35e85fbb7da73f9 (diff) | |
Refactor tests to use stop() and assert() instead of io.error/io.done
Gate assert, printf, stop by reset
Fix testbenches that never worked
Change simulation prints to display cycle at which test was signaled to end, not when simulator stops
Better documentation for Counter
Diffstat (limited to 'src/test/scala/chiselTests/ComplexAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ComplexAssign.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index bbd3d6c2..02f0e1ac 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -37,13 +37,13 @@ class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends Basic dut.io.e := Vec(enList.map(Bool(_)))(cnt) val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0)) val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0)) - when(!re_correct || !im_correct) { - io.done := Bool(true); io.error := cnt - } .elsewhen(wrap) { io.done := Bool(true) } + assert(re_correct && im_correct) + when(wrap) { + stop() + } } class ComplexAssignSpec extends ChiselPropSpec { - property("All complex assignments should return the correct result") { forAll(enSequence(2), safeUInts, safeUInts) { (en: List[Boolean], re: Int, im: Int) => assert(execute{ new ComplexAssignTester(en, re, im) }) |
