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authorducky2016-11-17 13:06:57 -0800
committerducky2016-11-21 13:31:12 -0800
commit73906fcc796b259c81d5df7733968b77fbb81ba8 (patch)
tree5f85e2e3cbf4753ddb4e8fa1014c465fa7005555 /src/test/scala/chiselTests/ComplexAssign.scala
parent54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (diff)
All remaining automatable regex re-styles
Diffstat (limited to 'src/test/scala/chiselTests/ComplexAssign.scala')
-rw-r--r--src/test/scala/chiselTests/ComplexAssign.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index f7484501..a13ec959 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -36,7 +36,7 @@ class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends Basic
val dut = Module(new ComplexAssign(32))
dut.io.in.re := re.asUInt
dut.io.in.im := im.asUInt
- dut.io.e := Vec(enList.map(Bool(_)))(cnt)
+ dut.io.e := Vec(enList.map(_.asBool))(cnt)
val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U)
val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U)
assert(re_correct && im_correct)