summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/CompatibilitySpec.scala
diff options
context:
space:
mode:
authorJack Koenig2021-01-21 22:50:12 -0800
committerGitHub2021-01-21 22:50:12 -0800
commitdd6871b8b3f2619178c2a333d9d6083805d99e16 (patch)
tree825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/CompatibilitySpec.scala
parent616256c35cb7de8fcd97df56af1986b747abe54d (diff)
parent53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff)
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')
-rw-r--r--src/test/scala/chiselTests/CompatibilitySpec.scala14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 50213d4d..6a77c821 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -239,6 +239,20 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
ChiselStage.elaborate { new RequireIOWrapModule() }
}
+ "A Module without val io" should "throw an exception" in {
+ class ModuleWithoutValIO extends Module {
+ val foo = new Bundle {
+ val in = UInt(width = 32).asInput
+ val out = Bool().asOutput
+ }
+ foo.out := foo.in(1)
+ }
+ val e = intercept[Exception](
+ ChiselStage.elaborate { new ModuleWithoutValIO }
+ )
+ e.getMessage should include("must have a 'val io' Bundle")
+ }
+
"A Module connecting output as source to input as sink when compiled with the Chisel compatibility package" should "not throw an exception" in {
class SimpleModule extends Module {