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authorJack Koenig2017-08-15 14:44:59 -0700
committerJack Koenig2017-08-15 18:59:25 -0700
commit90e775b1228765ce7f345716fa215f72b97816a9 (patch)
tree73be4079fb5820cbae7ae7b788f43e1e2537f2c4 /src/test/scala/chiselTests/CompatibilitySpec.scala
parentc87145bc61a729bb035428d527c5787c174c5256 (diff)
Make .dir give correct direction for Module io in compatibility
Diffstat (limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')
-rw-r--r--src/test/scala/chiselTests/CompatibilitySpec.scala54
1 files changed, 43 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index abbc040a..52a93aed 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -11,17 +11,26 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
behavior of "Chisel compatibility layer"
it should "accept direction arguments" in {
- val directionArgument: Direction = Gen.oneOf(INPUT, OUTPUT, NODIR).sample.get
- val b = Bool(directionArgument)
- b shouldBe a [Bool]
- b.getWidth shouldEqual 1
- b.dir shouldEqual(directionArgument)
- // Choose a random width
- val width = Gen.choose(1, 2048).sample.get
- val u = UInt(directionArgument, width)
- u shouldBe a [UInt]
- u.getWidth shouldEqual width
- u.dir shouldEqual(directionArgument)
+ elaborate(new Module {
+ // Choose a random direction
+ val directionArgument: Direction = Gen.oneOf(INPUT, OUTPUT, NODIR).sample.get
+ val expectedDirection = directionArgument match {
+ case NODIR => OUTPUT
+ case other => other
+ }
+ // Choose a random width
+ val width = Gen.choose(1, 2048).sample.get
+ val io = new Bundle {
+ val b = Bool(directionArgument)
+ val u = UInt(directionArgument, width)
+ }
+ io.b shouldBe a [Bool]
+ io.b.getWidth shouldEqual 1
+ io.b.dir shouldEqual (expectedDirection)
+ io.u shouldBe a [UInt]
+ io.u.getWidth shouldEqual width
+ io.u.dir shouldEqual (expectedDirection)
+ })
}
it should "accept single argument U/SInt factory methods" in {
@@ -260,4 +269,27 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks
io.out := RegEnable(io.in(0), true.B)
})
}
+
+ "Data.dir" should "give the correct direction for io" in {
+ import Chisel._
+ elaborate(new Module {
+ val io = (new Bundle {
+ val foo = Bool(OUTPUT)
+ val bar = Bool().flip
+ }).flip
+ Chisel.assert(io.foo.dir == INPUT)
+ Chisel.assert(io.bar.dir == OUTPUT)
+ })
+ }
+
+ // Note: This is a regression (see https://github.com/freechipsproject/chisel3/issues/668)
+ it should "fail for Chisel types" in {
+ import Chisel._
+ an [chisel3.core.Binding.ExpectedHardwareException] should be thrownBy {
+ elaborate(new Module {
+ val io = new Bundle { }
+ UInt(INPUT).dir
+ })
+ }
+ }
}