Use ChiselStage in Tests

This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:

- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
  methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

1 files changed, 31 insertions, 30 deletions

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 9d509cf3..09ec40ee 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -2,6 +2,7 @@
 
 package chiselTests
 
+import chisel3.stage.ChiselStage
 import chisel3.testers.BasicTester
 
 import org.scalacheck.Gen
@@ -17,13 +18,13 @@ object CompatibilityCustomCompileOptions {
   }
 }
 
-class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyChecks {
+class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyChecks with Utils {
   import Chisel._
 
   behavior of "Chisel compatibility layer"
 
   it should "accept direction arguments" in {
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       // Choose a random direction
       val directionArgument: Direction = Gen.oneOf(INPUT, OUTPUT, NODIR).sample.get
       val expectedDirection = directionArgument match {
@@ -126,7 +127,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       Valid(data) shouldBe a [ValidIO[UInt]]
       Pipe(Wire(Valid(data)), 2) shouldBe a [ValidIO[UInt]]
     }
-    elaborate { new Dummy }
+    ChiselStage.elaborate { new Dummy }
   }
   // Verify we can elaborate a design expressed in Chisel2
   class Chisel2CompatibleRisc extends Module {
@@ -178,11 +179,11 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
   }
 
   it should "Chisel2CompatibleRisc should elaborate" in {
-    elaborate { new Chisel2CompatibleRisc }
+    ChiselStage.elaborate { new Chisel2CompatibleRisc }
   }
 
   it should "not try to assign directions to Analog" in {
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = new Bundle {
         val port = chisel3.experimental.Analog(32.W)
       }
@@ -210,7 +211,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       }
       io.out := io.in
     }
-    elaborate { new ConnectFieldMismatchModule() }
+    ChiselStage.elaborate { new ConnectFieldMismatchModule() }
   }
 
   "A Module in which a Reg is created with a bound type when compiled with the Chisel compatibility package" should "not throw an exception" in {
@@ -222,7 +223,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       }
       val badReg = Reg(UInt(7, width=4))
     }
-    elaborate { new CreateRegFromBoundTypeModule() }
+    ChiselStage.elaborate { new CreateRegFromBoundTypeModule() }
   }
 
   "A Module with unwrapped IO when compiled with the Chisel compatibility package" should "not throw an exception" in {
@@ -234,7 +235,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       }
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    ChiselStage.elaborate { new RequireIOWrapModule() }
   }
 
   "A Module connecting output as source to input as sink when compiled with the Chisel compatibility package" should "not throw an exception" in {
@@ -249,7 +250,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       val child = Module(new SimpleModule)
       io.in := child.io.out
     }
-    elaborate { new SwappedConnectionModule() }
+    ChiselStage.elaborate { new SwappedConnectionModule() }
   }
 
   "A Module with directionless connections when compiled with the Chisel compatibility package" should "not throw an exception" in {
@@ -268,12 +269,12 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       val child = Module(new SimpleModule)
       b := child.noDir
     }
-    elaborate { new DirectionLessConnectionModule() }
+    ChiselStage.elaborate { new DirectionLessConnectionModule() }
   }
 
   "Vec ports" should "give default directions to children so they can be used in chisel3.util" in {
     import Chisel._
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = new Bundle {
         val in = Vec(1, UInt(width = 8)).flip
         val out = UInt(width = 8)
@@ -284,7 +285,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   "Reset" should "still walk, talk, and quack like a Bool" in {
     import Chisel._
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = new Bundle {
         val in = Bool(INPUT)
         val out = Bool(OUTPUT)
@@ -295,7 +296,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   "Data.dir" should "give the correct direction for io" in {
     import Chisel._
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = (new Bundle {
         val foo = Bool(OUTPUT)
         val bar = Bool().flip
@@ -308,8 +309,8 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
   // Note: This is a regression (see https://github.com/freechipsproject/chisel3/issues/668)
   it should "fail for Chisel types" in {
     import Chisel._
-    an [chisel3.ExpectedHardwareException] should be thrownBy {
-      elaborate(new Module {
+    an [chisel3.ExpectedHardwareException] should be thrownBy extractCause[chisel3.ExpectedHardwareException] {
+      ChiselStage.elaborate(new Module {
         val io = new Bundle { }
         UInt(INPUT).dir
       })
@@ -318,7 +319,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   "Mux return value" should "be able to be used on the RHS" in {
     import Chisel._
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val gen = new Bundle { val foo = UInt(width = 8) }
       val io = new Bundle {
         val a = Vec(2, UInt(width = 8)).asInput
@@ -336,7 +337,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   "Chisel3 IO constructs" should "be useable in Chisel2" in {
     import Chisel._
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = IO(new Bundle {
         val in = Input(Bool())
         val foo = Output(Bool())
@@ -366,7 +367,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       // (UInt(4) != bp) shouldBe a [Bool]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Enum"
@@ -389,7 +390,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       }.getMessage should include ("Bit width may no longer be specified for enums")
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Queue"
@@ -405,7 +406,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       val explicit = Module(new Queue(UInt(), 4, false, false, Bool(true)))
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "LFSR16"
@@ -424,7 +425,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       lfsr.getWidth should be (16)
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Mem"
@@ -442,7 +443,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       memInt shouldBe a [Mem[SInt]]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "SeqMem"
@@ -460,7 +461,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       seqMemInt shouldBe a [SeqMem[UInt]]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "debug"
@@ -473,7 +474,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       debug(data)
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Data methods"
@@ -491,7 +492,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       Vec.fill(4)(wire).toBits.getWidth should be (wire.getWidth * 4)
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Wire"
@@ -513,7 +514,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       third shouldBe a [UInt]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "Vec"
@@ -562,7 +563,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       UInt(1).toBool shouldBe a [Bool]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "UInt"
@@ -575,7 +576,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       (UInt(1) != UInt(1)) shouldBe a [Bool]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   behavior of "SInt"
@@ -588,13 +589,13 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       (SInt(-1) != SInt(-1)) shouldBe a [Bool]
     }
 
-    elaborate(new Foo)
+    ChiselStage.elaborate(new Foo)
   }
 
   it should "properly propagate custom compileOptions in Chisel.Module" in {
     import CompatibilityCustomCompileOptions._
     var result: Foo = null
-    elaborate({result = new Foo; result})
+    ChiselStage.elaborate({result = new Foo; result})
     result.compileOptions should be theSameInstanceAs (customCompileOptions)
   }