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authorJack2022-07-30 22:41:15 +0000
committerJack2022-07-30 22:41:15 +0000
commit4cd44fa4dab370fcc5c20bcacc1fa0ee02327252 (patch)
tree05730be260feca0d2a870c4bb88325d36631a8fc /src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
parentfe9635ef21bad233945617a24ab16cfa4055f2d1 (diff)
parentbced77045c8fc5db37e40b159c49220929e15d46 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala')
-rw-r--r--src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala39
1 files changed, 39 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 70dcda48..1e199297 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -351,4 +351,43 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
compile(new Top(true))
compile(new Top(false))
}
+
+ "A unidirectional but flipped Bundle with something close to NotStrict compileOptions, but not exactly" should "bulk connect in import chisel3._ code correctly" in {
+ object Compat {
+ import Chisel.{defaultCompileOptions => _, _}
+ // arbitrary thing to make this *not* exactly NotStrict
+ implicit val defaultCompileOptions = new chisel3.ExplicitCompileOptions.CompileOptionsClass(
+ connectFieldsMustMatch = false,
+ declaredTypeMustBeUnbound = false,
+ dontTryConnectionsSwapped = false,
+ dontAssumeDirectionality = false,
+ checkSynthesizable = false,
+ explicitInvalidate = false,
+ inferModuleReset = true // different from NotStrict, to ensure case class equivalence to NotStrict is false
+ ) {
+ override def emitStrictConnects = false
+ }
+
+ class MyBundle(extraFlip: Boolean) extends Bundle {
+ private def maybeFlip[T <: Data](t: T): T = if (extraFlip) t.flip else t
+ val foo = maybeFlip(new Bundle {
+ val bar = UInt(INPUT, width = 8)
+ })
+ }
+ }
+ import chisel3._
+ import Compat.{defaultCompileOptions => _, _}
+ class Top(extraFlip: Boolean) extends RawModule {
+ val port = IO(new MyBundle(extraFlip))
+ val wire = Wire(new MyBundle(extraFlip))
+ port <> DontCare
+ wire <> DontCare
+ port <> wire
+ wire <> port
+ port.foo <> wire.foo
+ wire.foo <> port.foo
+ }
+ compile(new Top(true))
+ compile(new Top(false))
+ }
}