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| author | Jack Koenig | 2021-01-21 22:50:12 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-21 22:50:12 -0800 |
| commit | dd6871b8b3f2619178c2a333d9d6083805d99e16 (patch) | |
| tree | 825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/CloneModuleSpec.scala | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
| parent | 53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff) | |
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/CloneModuleSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/CloneModuleSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala index 7f3ef854..e54ef1c2 100644 --- a/src/test/scala/chiselTests/CloneModuleSpec.scala +++ b/src/test/scala/chiselTests/CloneModuleSpec.scala @@ -8,7 +8,7 @@ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil} import chisel3.experimental.{CloneModuleAsRecord, IO} import chisel3.testers.BasicTester -class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule { +class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends Module { val clk = IO(Input(Clock())) val rst = IO(Input(Reset())) val enq = IO(Flipped(EnqIO(gen))) |