diff options
| author | Jack Koenig | 2022-01-10 16:32:51 -0800 |
|---|---|---|
| committer | GitHub | 2022-01-10 16:32:51 -0800 |
| commit | 2b48fd15a7711dcd44334fbbc538667a102a581a (patch) | |
| tree | 4b4766347c3943d65c13e5de2d139b14821eec61 /src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala | |
| parent | 92e77a97af986629766ac9038f0ebc8ab9a48fa1 (diff) | |
| parent | bff8dc0738adafa1176f6959a33ad86f6373c558 (diff) | |
Merge pull request #2246 from chipsalliance/scalafmt
Add scalafmt configuration and apply it.
Diffstat (limited to 'src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala index 40358d11..451ba885 100644 --- a/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala +++ b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala @@ -38,7 +38,7 @@ class ChiselTestUtilitiesSpec extends ChiselFlatSpec { } it should "error if the expected width is wrong" in { - a [TestFailedException] shouldBe thrownBy { + a[TestFailedException] shouldBe thrownBy { assertInferredWidth(8) { val w = Wire(UInt()) w := 2.U(2.W) |