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authorSchuyler Eldridge2020-03-19 14:36:13 -0400
committerGitHub2020-03-19 14:36:13 -0400
commitb8a8d792a0e06520eb1f2acf94e149425234bd3b (patch)
treea0eef32ce759a2c98680ff3c2b8fbde37a97e296 /src/test/scala/chiselTests/ChiselSpec.scala
parentd83235f635e4b048c063c8314e1340bca2db395f (diff)
parent3171cdf8472d50a4bcc6011c9b7786199a780514 (diff)
Merge pull request #1374 from freechipsproject/dont-wrap-elaboration-annotations
Don't wrap elaboration annotations
Diffstat (limited to 'src/test/scala/chiselTests/ChiselSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ChiselSpec.scala5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 9af7e88f..be1b2d60 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -7,7 +7,6 @@ import org.scalatest.prop._
import org.scalacheck._
import chisel3._
import chisel3.testers._
-import firrtl.options.OptionsException
import firrtl.{AnnotationSeq, CommonOptions, ExecutionOptionsManager, FirrtlExecutionFailure, FirrtlExecutionSuccess, HasFirrtlOptions}
import firrtl.util.BackendCompilationUtilities
import java.io.ByteArrayOutputStream
@@ -100,7 +99,7 @@ class ChiselTestUtilitiesSpec extends ChiselFlatSpec {
import org.scalatest.exceptions.TestFailedException
// Who tests the testers?
"assertKnownWidth" should "error when the expected width is wrong" in {
- val caught = intercept[OptionsException] {
+ val caught = intercept[ChiselException] {
assertKnownWidth(7) {
Wire(UInt(8.W))
}
@@ -123,7 +122,7 @@ class ChiselTestUtilitiesSpec extends ChiselFlatSpec {
}
"assertInferredWidth" should "error if the width is known" in {
- val caught = intercept[OptionsException] {
+ val caught = intercept[ChiselException] {
assertInferredWidth(8) {
Wire(UInt(8.W))
}