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authorJack Koenig2018-02-28 17:40:53 -0800
committerGitHub2018-02-28 17:40:53 -0800
commit46553432aaf65cff131e59081d57dabe16c2ab55 (patch)
tree2a64125046b36808a5a89c18f98204394c27ccd8 /src/test/scala/chiselTests/ChiselSpec.scala
parent97871178cb511063965f971b768f91c289c4776f (diff)
Refactor Annotations (#767)
* Generalize ChiselAnnotation This allows us to delay creation of Annotations till elaboration is complete. Also update all annotation-related code. * Add RunFirrtlTransform Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old ChiselAnnotation (now called ChiselLegacyAnnotation) * Use unique test directories in ChiselRunners.compile
Diffstat (limited to 'src/test/scala/chiselTests/ChiselSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ChiselSpec.scala6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 14672d68..661cf00e 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -16,9 +16,10 @@ import firrtl.{
FirrtlExecutionSuccess,
FirrtlExecutionFailure
}
+import firrtl.util.BackendCompilationUtilities
/** Common utility functions for Chisel unit tests. */
-trait ChiselRunners extends Assertions {
+trait ChiselRunners extends Assertions with BackendCompilationUtilities {
def runTester(t: => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = {
TesterDriver.execute(() => t, additionalVResources)
}
@@ -43,9 +44,10 @@ trait ChiselRunners extends Assertions {
* @return the Verilog code as a string.
*/
def compile(t: => RawModule): String = {
+ val testDir = createTestDirectory(this.getClass.getSimpleName)
val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions
with HasChiselExecutionOptions {
- commonOptions = CommonOptions(targetDirName = "test_run_dir")
+ commonOptions = CommonOptions(targetDirName = testDir.toString)
}
Driver.execute(manager, () => t) match {