diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/BundleWire.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/BundleWire.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BundleWire.scala | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 830fb7e4..3b58d52a 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -11,12 +11,12 @@ class Coord extends Bundle { class BundleWire(n: Int) extends Module { val io = IO(new Bundle { - val in = Input(new Coord) + val in = Input(new Coord) val outs = Output(Vec(n, new Coord)) }) val coords = Wire(Vec(n, new Coord)) for (i <- 0 until n) { - coords(i) := io.in + coords(i) := io.in io.outs(i) := coords(i) } } @@ -57,14 +57,13 @@ class BundleWireSpec extends ChiselPropSpec { property("All vec elems should match the inputs") { forAll(vecSizes, safeUInts, safeUInts) { (n: Int, x: Int, y: Int) => - assertTesterPasses{ new BundleWireTester(n, x, y) } + assertTesterPasses { new BundleWireTester(n, x, y) } } } } class BundleToUIntSpec extends ChiselPropSpec { property("Bundles with same data but different, underlying elements should compare as UInt") { - assertTesterPasses( new BundleToUnitTester ) + assertTesterPasses(new BundleToUnitTester) } } - |
