diff options
| author | Richard Lin | 2019-04-01 14:00:55 -0700 |
|---|---|---|
| committer | GitHub | 2019-04-01 14:00:55 -0700 |
| commit | 9f77bf54543724594711f0455ef91f51edfbd22e (patch) | |
| tree | d61325c120a65ad6e12e1772dc92ceef86f1a872 /src/test/scala/chiselTests/BundleSpec.scala | |
| parent | 69e8250dd47210cee809c9ae231c1e320d76c084 (diff) | |
Detect bundle aliasing (#1050)
Diffstat (limited to 'src/test/scala/chiselTests/BundleSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BundleSpec.scala | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index 4fc7d7d0..d30b64b3 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -115,4 +115,17 @@ class BundleSpec extends ChiselFlatSpec with BundleSpecUtils { } } } + + "Bundles" should "not have aliased fields" in { + (the[ChiselException] thrownBy { + elaborate { new Module { + val io = IO(Output(new Bundle { + val a = UInt(8.W) + val b = a + })) + io.a := 0.U + io.b := 1.U + } } + }).getMessage should include("aliased fields") + } } |
