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| author | Richard Lin | 2017-04-26 17:52:29 -0700 |
|---|---|---|
| committer | GitHub | 2017-04-26 17:52:29 -0700 |
| commit | 36718cf6040990f2be9ab143adb1d3c519e9d983 (patch) | |
| tree | 34ae121faf999bb962f5257c26de651bd08ecf04 /src/test/scala/chiselTests/BundleSpec.scala | |
| parent | 7449fdc9043708e426aeb8b12b30226db9e47a80 (diff) | |
Deprecate fromBits and clock/reset constructors (#583)
Diffstat (limited to 'src/test/scala/chiselTests/BundleSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BundleSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index 0a6866d3..bb1393bc 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -43,7 +43,7 @@ trait BundleSpecUtils { assert(uint.getWidth == 32) // elaboration time assert(uint === "h12345678".asUInt(32.W)) // Back to Bundle - val bundle2 = (new BundleFooBar).fromBits(uint) + val bundle2 = uint.asTypeOf(new BundleFooBar) assert(0x1234.U === bundle2.foo) assert(0x5678.U === bundle2.bar) stop() |