Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 27 insertions, 21 deletions

diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala
index d9f82e6d..720f877f 100644
--- a/src/test/scala/chiselTests/BundleSpec.scala
+++ b/src/test/scala/chiselTests/BundleSpec.scala
@@ -61,13 +61,13 @@ class BundleSpec extends ChiselFlatSpec with BundleSpecUtils with Utils {
   }
 
   "Bulk connect on Bundles" should "check that the fields match" in {
-    (the [ChiselException] thrownBy extractCause[ChiselException] {
+    (the[ChiselException] thrownBy extractCause[ChiselException] {
       ChiselStage.elaborate { new MyModule(new BundleFooBar, new BundleFoo) }
-    }).getMessage should include ("Right Record missing field")
+    }).getMessage should include("Right Record missing field")
 
-    (the [ChiselException] thrownBy extractCause[ChiselException] {
+    (the[ChiselException] thrownBy extractCause[ChiselException] {
       ChiselStage.elaborate { new MyModule(new BundleFoo, new BundleFooBar) }
-    }).getMessage should include ("Left Record missing field")
+    }).getMessage should include("Left Record missing field")
   }
 
   "Bundles" should "not be able to use Seq for constructing hardware" in {
@@ -120,33 +120,39 @@ class BundleSpec extends ChiselFlatSpec with BundleSpecUtils with Utils {
     }
 
     (the[ChiselException] thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate { new Module {
-        val io = IO(Output(new AliasedBundle))
-        io.a := 0.U
-        io.b := 1.U
-      } }
+      ChiselStage.elaborate {
+        new Module {
+          val io = IO(Output(new AliasedBundle))
+          io.a := 0.U
+          io.b := 1.U
+        }
+      }
     }).getMessage should include("contains aliased fields named (a,b),(c,d)")
   }
 
   "Bundles" should "not have bound hardware" in {
     (the[ChiselException] thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate { new Module {
-        class MyBundle(val foo: UInt) extends Bundle
-        val in  = IO(Input(new MyBundle(123.U))) // This should error: value passed in instead of type
-        val out = IO(Output(new MyBundle(UInt(8.W))))
+      ChiselStage.elaborate {
+        new Module {
+          class MyBundle(val foo: UInt) extends Bundle
+          val in = IO(Input(new MyBundle(123.U))) // This should error: value passed in instead of type
+          val out = IO(Output(new MyBundle(UInt(8.W))))
 
-        out := in
-      } }
+          out := in
+        }
+      }
     }).getMessage should include("must be a Chisel type, not hardware")
   }
   "Bundles" should "not recursively contain aggregates with bound hardware" in {
     (the[ChiselException] thrownBy extractCause[ChiselException] {
-      ChiselStage.elaborate { new Module {
-        class MyBundle(val foo: UInt) extends Bundle
-        val out = IO(Output(Vec(2, UInt(8.W))))
-        val in  = IO(Input(new MyBundle(out(0)))) // This should error: Bound aggregate passed
-        out := in
-      } }
+      ChiselStage.elaborate {
+        new Module {
+          class MyBundle(val foo: UInt) extends Bundle
+          val out = IO(Output(Vec(2, UInt(8.W))))
+          val in = IO(Input(new MyBundle(out(0)))) // This should error: Bound aggregate passed
+          out := in
+        }
+      }
     }).getMessage should include("must be a Chisel type, not hardware")
   }
   "Unbound bundles sharing a field" should "not error" in {