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| author | mergify[bot] | 2022-10-23 19:01:43 +0000 |
|---|---|---|
| committer | GitHub | 2022-10-23 19:01:43 +0000 |
| commit | d997acb05e5a307afb7c9ad4c136b9b4e1506efc (patch) | |
| tree | 57756efa278459f31cbadce539f6f1a0d7e679f7 /src/test/scala/chiselTests/BulkConnectSpec.scala | |
| parent | 80b3b28f451efa85be50994f732599f043f83d86 (diff) | |
Don't invalidate ExtModule ports in an explicitInvalidate = true context (backport #2795) (#2799)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context
ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.
(cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d)
# Conflicts:
# core/src/main/scala/chisel3/BlackBox.scala
* Resolve backport conflicts
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/BulkConnectSpec.scala')
0 files changed, 0 insertions, 0 deletions