summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/BulkConnectSpec.scala
diff options
context:
space:
mode:
authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /src/test/scala/chiselTests/BulkConnectSpec.scala
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/BulkConnectSpec.scala')
-rw-r--r--src/test/scala/chiselTests/BulkConnectSpec.scala15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index 281890d4..0a1616d3 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -54,7 +54,15 @@ class BulkConnectSpec extends ChiselPropSpec {
})
chirrtl should include("out.buzz.foo <= in.buzz.foo")
+ chirrtl should include("out.fizz <= in.fizz")
+ chirrtl should include("deq.bits <- enq.bits")
+ chirrtl should include("deq.valid <= enq.valid")
+ chirrtl should include("enq.ready <= deq.ready")
+
chirrtl shouldNot include("deq <= enq")
+ chirrtl shouldNot include("deq.bits.foo <= enq.bits.foo")
+ chirrtl shouldNot include("deq.bits.foo <- enq.bits.foo")
+ chirrtl shouldNot include("deq.bits.bar")
}
property("Chisel connects should not emit FIRRTL bulk connects between differing FIRRTL types") {
@@ -74,7 +82,9 @@ class BulkConnectSpec extends ChiselPropSpec {
out <> in
})
// out <- in is illegal FIRRTL
- chirrtl should include("out.foo.bar <= in.foo.bar")
+ exactly(2, chirrtl.split('\n')) should include("out.foo.bar <= in.foo.bar")
+ chirrtl shouldNot include("out <= in")
+ chirrtl shouldNot include("out <- in")
}
property("Chisel connects should not emit a FIRRTL bulk connect for a bidirectional MonoConnect") {
@@ -91,6 +101,9 @@ class BulkConnectSpec extends ChiselPropSpec {
})
chirrtl shouldNot include("wire <= enq")
+ chirrtl should include("wire.bits <= enq.bits")
+ chirrtl should include("wire.valid <= enq.valid")
+ chirrtl should include("wire.ready <= enq.ready")
chirrtl should include("deq <= enq")
}