diff options
| author | Schuyler Eldridge | 2020-06-22 20:34:46 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-22 20:34:46 -0400 |
| commit | 9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch) | |
| tree | ac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/BoringUtilsSpec.scala | |
| parent | d099d01ae6b11d8befdf7b32ab74c3167a552984 (diff) | |
| parent | b5e59895e13550006fd8e951b7e9483de00f82dd (diff) | |
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/BoringUtilsSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BoringUtilsSpec.scala | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 755ba60b..997466c0 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -8,10 +8,12 @@ import chisel3.testers.BasicTester import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform} import chisel3.util.experimental.BoringUtils -import firrtl.{CircuitForm, CircuitState, ChirrtlForm, Transform} +import firrtl.{CircuitForm, CircuitState, ChirrtlForm, DependencyAPIMigration, Transform} import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.Dependency import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} -import firrtl.passes.wiring.WiringException +import firrtl.passes.wiring.{WiringException, WiringTransform} +import firrtl.stage.Forms abstract class ShouldntAssertTester(cyclesToWait: BigInt = 4) extends BasicTester { val dut: BaseModule @@ -19,11 +21,14 @@ abstract class ShouldntAssertTester(cyclesToWait: BigInt = 4) extends BasicTeste when (done) { stop() } } -class StripNoDedupAnnotation extends Transform { - def inputForm: CircuitForm = ChirrtlForm - def outputForm: CircuitForm = ChirrtlForm - def execute(state: CircuitState): CircuitState = +class StripNoDedupAnnotation extends Transform with DependencyAPIMigration { + override def prerequisites = Forms.ChirrtlForm + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Dependency[WiringTransform] +: Forms.ChirrtlEmitters + override def invalidates(a: Transform) = false + def execute(state: CircuitState): CircuitState = { state.copy(annotations = state.annotations.filter{ case _: NoDedupAnnotation => false; case _ => true }) + } } class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { |
