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authorJack Koenig2021-01-20 13:46:48 -0800
committerJack Koenig2021-01-21 15:36:55 -0800
commit5ece5aa8ac2716d66a6ed91e38a978049d8bf250 (patch)
treef83353530e836491bb9b770712f1b8ff3dac3942 /src/test/scala/chiselTests/BoringUtilsSpec.scala
parent616256c35cb7de8fcd97df56af1986b747abe54d (diff)
Rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/BoringUtilsSpec.scala')
-rw-r--r--src/test/scala/chiselTests/BoringUtilsSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 0500ac23..39859581 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -71,7 +71,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
out := x
}
- class Top(val width: Int) extends MultiIOModule {
+ class Top(val width: Int) extends Module {
/* From the perspective of deduplication, all sources are identical and all sinks are identical. */
val sources = Seq.fill(3)(Module(new Source))
val sinks = Seq.fill(6)(Module(new Sink))