Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 21 insertions, 19 deletions

diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 39859581..9be2d75a 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -8,7 +8,7 @@ import chisel3.testers._
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.util.experimental.BoringUtils
 
-import firrtl.{CircuitForm, CircuitState, ChirrtlForm, DependencyAPIMigration, Transform}
+import firrtl.{ChirrtlForm, CircuitForm, CircuitState, DependencyAPIMigration, Transform}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.Dependency
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
@@ -18,7 +18,7 @@ import firrtl.stage.Forms
 abstract class ShouldntAssertTester(cyclesToWait: BigInt = 4) extends BasicTester {
   val dut: BaseModule
   val (_, done) = Counter(true.B, 2)
-  when (done) { stop() }
+  when(done) { stop() }
 }
 
 class StripNoDedupAnnotation extends Transform with DependencyAPIMigration {
@@ -27,14 +27,14 @@ class StripNoDedupAnnotation extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Dependency[WiringTransform] +: Forms.ChirrtlEmitters
   override def invalidates(a: Transform) = false
   def execute(state: CircuitState): CircuitState = {
-    state.copy(annotations = state.annotations.filter{ case _: NoDedupAnnotation => false; case _ => true })
+    state.copy(annotations = state.annotations.filter { case _: NoDedupAnnotation => false; case _ => true })
   }
 }
 
 class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
 
   class BoringInverter extends Module {
-    val io = IO(new Bundle{})
+    val io = IO(new Bundle {})
     val a = Wire(UInt(1.W))
     val notA = Wire(UInt(1.W))
     val b = Wire(UInt(1.W))
@@ -46,11 +46,13 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
     BoringUtils.addSink(b, "x")
   }
 
-  behavior of "BoringUtils.{addSink, addSource}"
+  behavior.of("BoringUtils.{addSink, addSource}")
 
   it should "connect two wires within a module" in {
-    runTester(new ShouldntAssertTester { val dut = Module(new BoringInverter) },
-      annotations = TesterDriver.verilatorOnly) should be (true)
+    runTester(
+      new ShouldntAssertTester { val dut = Module(new BoringInverter) },
+      annotations = TesterDriver.verilatorOnly
+    ) should be(true)
   }
 
   trait WireX { this: BaseModule =>
@@ -77,10 +79,10 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
     val sinks = Seq.fill(6)(Module(new Sink))
 
     /* Sources are differentiated by their input connections only. */
-    sources.zip(Seq(0, 1, 2)).map{ case (a, b) => a.in := b.U }
+    sources.zip(Seq(0, 1, 2)).map { case (a, b) => a.in := b.U }
 
     /* Sinks are differentiated by their post-boring outputs. */
-    sinks.zip(Seq(0, 1, 1, 2, 2, 2)).map{ case (a, b) => chisel3.assert(a.out === b.U) }
+    sinks.zip(Seq(0, 1, 1, 2, 2, 2)).map { case (a, b) => chisel3.assert(a.out === b.U) }
   }
 
   /** This is testing a complicated wiring pattern and exercising
@@ -95,22 +97,22 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
 
   trait FailViaDedup { this: TopTester =>
     case object FooAnnotation extends NoTargetAnnotation
-    chisel3.experimental.annotate(
-      new ChiselAnnotation with RunFirrtlTransform {
-        def toFirrtl: Annotation = FooAnnotation
-        def transformClass: Class[_ <: Transform] = classOf[StripNoDedupAnnotation] } )
+    chisel3.experimental.annotate(new ChiselAnnotation with RunFirrtlTransform {
+      def toFirrtl:       Annotation = FooAnnotation
+      def transformClass: Class[_ <: Transform] = classOf[StripNoDedupAnnotation]
+    })
   }
 
-  behavior of "BoringUtils.bore"
+  behavior.of("BoringUtils.bore")
 
   it should "connect across modules using BoringUtils.bore" in {
-    runTester(new TopTester, annotations = TesterDriver.verilatorOnly) should be (true)
+    runTester(new TopTester, annotations = TesterDriver.verilatorOnly) should be(true)
   }
 
   it should "throw an exception if NoDedupAnnotations are removed" in {
-    intercept[WiringException] { runTester(new TopTester with FailViaDedup,
-      annotations = Seq(TesterDriver.VerilatorBackend)) }
-      .getMessage should startWith ("Unable to determine source mapping for sink")
+    intercept[WiringException] {
+      runTester(new TopTester with FailViaDedup, annotations = Seq(TesterDriver.VerilatorBackend))
+    }.getMessage should startWith("Unable to determine source mapping for sink")
   }
 
   class InternalBore extends RawModule {
@@ -127,7 +129,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
   }
 
   it should "work for an internal (same module) BoringUtils.bore" in {
-    runTester(new InternalBoreTester, annotations = TesterDriver.verilatorOnly) should be (true)
+    runTester(new InternalBoreTester, annotations = TesterDriver.verilatorOnly) should be(true)
   }
 
 }