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authormergify[bot]2022-04-25 23:19:37 +0000
committerGitHub2022-04-25 23:19:37 +0000
commit3e551ef38fb4c01b9b46f45dc68c2d9f5c9e9acb (patch)
tree0e3b35f136fe778a712d37a1eeb3a4185781b9f8 /src/test/scala/chiselTests/BlackBox.scala
parent5a90f27ab1311994b4df73a85cd0facab3ae0b3a (diff)
Fix error message for BlackBox without val io <: Record (#2504) (#2505)
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/test/scala/chiselTests/BlackBox.scala')
-rw-r--r--src/test/scala/chiselTests/BlackBox.scala29
1 files changed, 28 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 27cdbbc4..f923a94a 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -145,6 +145,17 @@ class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawPara
})
}
+class BlackBoxNoIO extends BlackBox {
+ // Whoops! typo
+ val ioo = IO(new Bundle {
+ val out = Output(UInt(8.W))
+ })
+}
+
+class BlackBoxUIntIO extends BlackBox {
+ val io = IO(Output(UInt(8.W)))
+}
+
class BlackBoxWithParamsTester extends BasicTester {
val blackBoxOne = Module(new BlackBoxConstant(1))
val blackBoxFour = Module(new BlackBoxConstant(4))
@@ -192,7 +203,23 @@ class BlackBoxSpec extends ChiselFlatSpec {
assert(DataMirror.modulePorts(m) == Seq("in" -> m.io.in, "out" -> m.io.out))
})
}
- "A BlackBoxed using suggestName(\"io\")" should "work (but don't do this)" in {
+ "A BlackBox using suggestName(\"io\")" should "work (but don't do this)" in {
assertTesterPasses({ new BlackBoxTesterSuggestName }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly)
}
+
+ "A BlackBox with no 'val io'" should "give a reasonable error message" in {
+ (the[ChiselException] thrownBy {
+ ChiselStage.elaborate(new Module {
+ val inst = Module(new BlackBoxNoIO)
+ })
+ }).getMessage should include("must have a port named 'io' of type Record")
+ }
+
+ "A BlackBox with non-Record 'val io'" should "give a reasonable error message" in {
+ (the[ChiselException] thrownBy {
+ ChiselStage.elaborate(new Module {
+ val inst = Module(new BlackBoxUIntIO)
+ })
+ }).getMessage should include("must have a port named 'io' of type Record")
+ }
}