diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/BlackBox.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/BlackBox.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BlackBox.scala | 50 |
1 files changed, 15 insertions, 35 deletions
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index d3d52f96..27cdbbc4 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -5,7 +5,7 @@ package chiselTests import chisel3._ import chisel3.experimental._ import chisel3.stage.ChiselStage -import chisel3.testers.{TesterDriver, BasicTester} +import chisel3.testers.{BasicTester, TesterDriver} import chisel3.util._ class BlackBoxInverter extends BlackBox { @@ -120,8 +120,7 @@ class BlackBoxWithClockTester extends BasicTester { when(end) { stop() } } -class BlackBoxConstant(value: Int) extends BlackBox( - Map("VALUE" -> value, "WIDTH" -> log2Ceil(value + 1))) { +class BlackBoxConstant(value: Int) extends BlackBox(Map("VALUE" -> value, "WIDTH" -> log2Ceil(value + 1))) { require(value >= 0, "value must be a UInt!") val io = IO(new Bundle { val out = Output(UInt(log2Ceil(value + 1).W)) @@ -147,8 +146,8 @@ class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawPara } class BlackBoxWithParamsTester extends BasicTester { - val blackBoxOne = Module(new BlackBoxConstant(1)) - val blackBoxFour = Module(new BlackBoxConstant(4)) + val blackBoxOne = Module(new BlackBoxConstant(1)) + val blackBoxFour = Module(new BlackBoxConstant(4)) val blackBoxStringParamOne = Module(new BlackBoxStringParam("one")) val blackBoxStringParamTwo = Module(new BlackBoxStringParam("two")) val blackBoxRealParamOne = Module(new BlackBoxRealParam(1.0)) @@ -158,7 +157,7 @@ class BlackBoxWithParamsTester extends BasicTester { val (cycles, end) = Counter(true.B, 4) - assert(blackBoxOne.io.out === 1.U) + assert(blackBoxOne.io.out === 1.U) assert(blackBoxFour.io.out === 4.U) assert(blackBoxStringParamOne.io.out === 1.U) assert(blackBoxStringParamTwo.io.out === 2.U) @@ -172,47 +171,28 @@ class BlackBoxWithParamsTester extends BasicTester { class BlackBoxSpec extends ChiselFlatSpec { "A BlackBoxed inverter" should "work" in { - assertTesterPasses( - {new BlackBoxTester}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new BlackBoxTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } "A BlackBoxed with flipped IO" should "work" in { - assertTesterPasses( - {new BlackBoxFlipTester}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new BlackBoxFlipTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } "Multiple BlackBoxes" should "work" in { - assertTesterPasses( - {new MultiBlackBoxTester}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new MultiBlackBoxTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } "A BlackBoxed register" should "work" in { - assertTesterPasses( - {new BlackBoxWithClockTester}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new BlackBoxWithClockTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } "BlackBoxes with parameters" should "work" in { - assertTesterPasses( - {new BlackBoxWithParamsTester}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new BlackBoxWithParamsTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } "DataMirror.modulePorts" should "work with BlackBox" in { ChiselStage.elaborate(new Module { - val io = IO(new Bundle {}) - val m = Module(new BlackBoxPassthrough) - assert(DataMirror.modulePorts(m) == Seq("in" -> m.io.in, "out" -> m.io.out)) - } - ) + val io = IO(new Bundle {}) + val m = Module(new BlackBoxPassthrough) + assert(DataMirror.modulePorts(m) == Seq("in" -> m.io.in, "out" -> m.io.out)) + }) } "A BlackBoxed using suggestName(\"io\")" should "work (but don't do this)" in { - assertTesterPasses( - {new BlackBoxTesterSuggestName}, - Seq("/chisel3/BlackBoxTest.v"), - TesterDriver.verilatorOnly) + assertTesterPasses({ new BlackBoxTesterSuggestName }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly) } } |
