diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/BetterNamingTests.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/BetterNamingTests.scala')
| -rw-r--r-- | src/test/scala/chiselTests/BetterNamingTests.scala | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index a55d3e08..8fd1c11f 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -31,10 +31,14 @@ class IterableNaming extends NamedModuleTester { val seq = Seq.tabulate(3) { i => Seq.tabulate(2) { j => expectName(WireDefault((i * j).U), s"seq_${i}_${j}") } } - val optSet = Some(Set(expectName(WireDefault(0.U), "optSet_0"), - expectName(WireDefault(1.U), "optSet_1"), - expectName(WireDefault(2.U), "optSet_2"), - expectName(WireDefault(3.U), "optSet_3"))) + val optSet = Some( + Set( + expectName(WireDefault(0.U), "optSet_0"), + expectName(WireDefault(1.U), "optSet_1"), + expectName(WireDefault(2.U), "optSet_2"), + expectName(WireDefault(3.U), "optSet_3") + ) + ) val stack = { val s = mutable.Stack[Module]() @@ -62,7 +66,7 @@ class DigitFieldNamesInRecord extends NamedModuleTester { */ class BetterNamingTests extends ChiselFlatSpec { - behavior of "Better Naming" + behavior.of("Better Naming") it should "provide unique counters for each name" in { var module: PerNameIndexing = null @@ -77,7 +81,7 @@ class BetterNamingTests extends ChiselFlatSpec { } it should "allow digits to be field names in Records" in { - var module: DigitFieldNamesInRecord = null + var module: DigitFieldNamesInRecord = null ChiselStage.elaborate { module = new DigitFieldNamesInRecord; module } assert(module.getNameFailures() == Nil) } @@ -92,6 +96,6 @@ class BetterNamingTests extends ChiselFlatSpec { } val withLits = ChiselStage.emitChirrtl(new MyModule(true)) val noLits = ChiselStage.emitChirrtl(new MyModule(false)) - withLits should equal (noLits) + withLits should equal(noLits) } } |
