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| author | Jim Lawson | 2019-07-18 13:46:53 -0700 |
|---|---|---|
| committer | GitHub | 2019-07-18 13:46:53 -0700 |
| commit | ae784b6e9dde1a5692b37067573cfddc164cdf26 (patch) | |
| tree | d53a68a4e3f71d5ceeda0c41f2e558d1530ce776 /src/test/scala/chiselTests/AnalogSpec.scala | |
| parent | 8b8586087c0c8370773b453fb28ac5d426909e38 (diff) | |
Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)
* Add width utility functions to avoid incorrect usage of bare log2Ceil().
* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.
* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.
* Respond to comments - return in.bitLength - 0 (not 1) for 0
* Respond to comments - update wdith for signed 0; add explicit tests.
* Add comment expressing zero width wire assumption.
Diffstat (limited to 'src/test/scala/chiselTests/AnalogSpec.scala')
0 files changed, 0 insertions, 0 deletions