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authorRichard Lin2017-04-13 22:59:00 -0700
committerGitHub2017-04-13 22:59:00 -0700
commite07248b8f6022fafdb84f5d1c0ebe3fc90a5475a (patch)
treef2bb938fd35651b4fc7b88cbcd20e163cc75dd2e /src/test/scala/chiselTests/AnalogIntegrationSpec.scala
parent97902cdc53eec52aa0cd806b8cb49a0e3f2fb769 (diff)
Module Hierarchy Refactor (#469)
Diffstat (limited to 'src/test/scala/chiselTests/AnalogIntegrationSpec.scala')
-rw-r--r--src/test/scala/chiselTests/AnalogIntegrationSpec.scala15
1 files changed, 11 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
index 92f89e06..de717c4f 100644
--- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
+++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
@@ -31,11 +31,18 @@ class AnalogBlackBox(index: Int) extends BlackBox(Map("index" -> index)) {
val io = IO(new AnalogBlackBoxIO(1))
}
+// AnalogBlackBox wrapper, which extends Module to present the common io._ interface
+class AnalogBlackBoxModule(index: Int) extends Module {
+ val io = IO(new AnalogBlackBoxIO(1))
+ val impl = Module(new AnalogBlackBox(index))
+ io <> impl.io
+}
+
// Wraps up n blackboxes, connecing their buses and simply forwarding their ports up
class AnalogBlackBoxWrapper(n: Int, idxs: Seq[Int]) extends Module {
require(n > 0)
val io = IO(new AnalogBlackBoxIO(n))
- val bbs = idxs.map(i => Module(new AnalogBlackBox(i)))
+ val bbs = idxs.map(i => Module(new AnalogBlackBoxModule(i)))
io.bus <> bbs.head.io.bus // Always bulk connect io.bus to first bus
io.port <> bbs.flatMap(_.io.port) // Connect ports
attach(bbs.map(_.io.bus):_*) // Attach all the buses
@@ -58,9 +65,9 @@ abstract class AnalogDUTModule(numBlackBoxes: Int) extends Module {
class AnalogDUT extends AnalogDUTModule(5) { // 5 BlackBoxes
val mods = Seq(
Module(new AnalogBlackBoxWrapper(1, Seq(0))),
- Module(new AnalogBlackBox(1)),
+ Module(new AnalogBlackBoxModule(1)),
Module(new AnalogBlackBoxWrapper(2, Seq(2, 3))), // 2 blackboxes
- Module(new AnalogBlackBox(4))
+ Module(new AnalogBlackBoxModule(4))
)
// Connect all ports to top
io.ports <> mods.flatMap(_.io.port)
@@ -79,7 +86,7 @@ class AnalogDUT extends AnalogDUTModule(5) { // 5 BlackBoxes
class AnalogSmallDUT extends AnalogDUTModule(4) { // 4 BlackBoxes
val mods = Seq(
Module(new AnalogBlackBoxWrapper(1, Seq(0))),
- Module(new AnalogBlackBox(1)),
+ Module(new AnalogBlackBoxModule(1)),
Module(new AnalogBlackBoxWrapper(2, Seq(2, 3))) // 2 BlackBoxes
)
// Connect all ports to top