diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/AdderTree.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/AdderTree.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AdderTree.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/AdderTree.scala b/src/test/scala/chiselTests/AdderTree.scala index 171fa616..29ef97a4 100644 --- a/src/test/scala/chiselTests/AdderTree.scala +++ b/src/test/scala/chiselTests/AdderTree.scala @@ -10,14 +10,14 @@ class AdderTree[T <: Bits with Num[T]](genType: T, vecSize: Int) extends Module val numIn = Input(Vec(vecSize, genType)) val numOut = Output(genType) }) - io.numOut := io.numIn.reduceTree((a : T, b : T) => (a + b)) + io.numOut := io.numIn.reduceTree((a: T, b: T) => (a + b)) } class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends BasicTester { val genType = UInt(bitWidth.W) val dut = Module(new AdderTree(genType, numsToAdd.size)) dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W))) - val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_+_) % (1 << bitWidth)).asUInt(bitWidth.W) + val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W) assert(sumCorrect) stop() } @@ -27,7 +27,7 @@ class AdderTreeSpec extends ChiselPropSpec { forAll(safeUIntN(20)) { case (w: Int, v: List[Int]) => { whenever(v.size > 0 && w > 0) { - assertTesterPasses { new AdderTreeTester(w, v.map(x => math.abs(x) % ( 1 << w )).toList) } + assertTesterPasses { new AdderTreeTester(w, v.map(x => math.abs(x) % (1 << w)).toList) } } } } |
