summaryrefslogtreecommitdiff
path: root/src/test/scala/ChiselTests
diff options
context:
space:
mode:
authorHenry Cook2015-08-02 21:10:41 -0700
committerHenry Cook2015-08-02 21:10:41 -0700
commit320bedd50e2ec47ba9b0ca954c72fafd78a9b392 (patch)
tree7147b6ad144301727a22e42da80a76db059f2845 /src/test/scala/ChiselTests
parentc65fb24a586a377ec5018dfb8f41b5b899c0d13c (diff)
Make tests compile again
Diffstat (limited to 'src/test/scala/ChiselTests')
-rw-r--r--src/test/scala/ChiselTests/ComplexAssign.scala9
-rw-r--r--src/test/scala/ChiselTests/VendingMachine.scala2
2 files changed, 5 insertions, 6 deletions
diff --git a/src/test/scala/ChiselTests/ComplexAssign.scala b/src/test/scala/ChiselTests/ComplexAssign.scala
index bcc49543..886a2a7e 100644
--- a/src/test/scala/ChiselTests/ComplexAssign.scala
+++ b/src/test/scala/ChiselTests/ComplexAssign.scala
@@ -1,17 +1,16 @@
package ChiselTests
import Chisel._
-class Complex[T <: Data](val re: T, val im: T, dir: Direction = OUTPUT)
- extends Bundle(dir) {
+class Complex[T <: Data](val re: T, val im: T) extends Bundle {
override def cloneType: this.type =
- new Complex(re.cloneType, im.cloneType, dir).asInstanceOf[this.type]
+ new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
}
class ComplexAssign(W: Int) extends Module {
val io = new Bundle {
val e = new Bool(INPUT)
- val in = new Complex(Bits(width = W), Bits(width = W), INPUT)
- val out = new Complex(Bits(width = W), Bits(width = W), OUTPUT)
+ val in = new Complex(Bits(width = W), Bits(width = W)).asInput
+ val out = new Complex(Bits(width = W), Bits(width = W)).asOutput
}
when (io.e) {
val w = Wire(new Complex(Bits(width = W), Bits(width = W)))
diff --git a/src/test/scala/ChiselTests/VendingMachine.scala b/src/test/scala/ChiselTests/VendingMachine.scala
index 787f7e33..097ee992 100644
--- a/src/test/scala/ChiselTests/VendingMachine.scala
+++ b/src/test/scala/ChiselTests/VendingMachine.scala
@@ -6,7 +6,7 @@ class VendingMachine extends Module {
val nickel = Bool(dir = INPUT)
val dime = Bool(dir = INPUT)
val valid = Bool(dir = OUTPUT) }
- val c = Lit(5, 3){ UInt() }
+ val c = UInt(5, width = 3)
val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
val state = Reg(init = sIdle)
when (state === sIdle) {