diff options
| author | Henry Cook | 2015-08-12 19:32:43 -0700 |
|---|---|---|
| committer | Henry Cook | 2015-08-12 19:32:57 -0700 |
| commit | 85d7403f9bf7bc2b3520f924736c237f21f70ebd (patch) | |
| tree | 64560f779063a419395a2fb8a31ea52c52af4404 /src/test/scala/ChiselTests/main.scala | |
| parent | 7e69966362b1dbd9835695250494857f3a3767c8 (diff) | |
being to convert tests to scala-test; tests compile and run
Diffstat (limited to 'src/test/scala/ChiselTests/main.scala')
| -rw-r--r-- | src/test/scala/ChiselTests/main.scala | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/src/test/scala/ChiselTests/main.scala b/src/test/scala/ChiselTests/main.scala deleted file mode 100644 index 14745d5a..00000000 --- a/src/test/scala/ChiselTests/main.scala +++ /dev/null @@ -1,41 +0,0 @@ -package ChiselTests -import Chisel._ -import Chisel.testers._ - -object MiniChisel { - def main(gargs: Array[String]): Unit = { - if (gargs.length < 1) - println("Need an argument") - val name = gargs(0) - val margs = Array("--targetDir", "generated") - val args = margs ++ gargs.slice(1, gargs.length) - name match { - case "EnableShiftRegister" => chiselMainTest(args, () => Module(new EnableShiftRegister))(c => new EnableShiftRegisterTester(c)) - case "MemorySearch" => chiselMainTest(args, () => Module(new MemorySearch))(c => new MemorySearchTester(c)) - case "VecApp" => chiselMainTest(args, () => Module(new VecApp(4,8)))(c => new VecAppTester(c)) - case "Counter" => chiselMainTest(args, () => Module(new Counter))(c => new CounterTester(c)) - case "Tbl" => chiselMainTest(args, () => Module(new Tbl))(c => new TblTester(c)) - case "LFSR16" => chiselMainTest(args, () => Module(new LFSR16))(c => new LFSR16Tester(c)) - case "Mul" => chiselMainTest(args, () => Module(new Mul(2)))(c => new MulTester(c)) - case "Decoder" => chiselMainTest(args, () => Module(new Decoder))(c => new DecoderTester(c)) - case "VecShiftRegister" => chiselMainTest(args, () => Module(new VecShiftRegister))(c => new VecShiftRegisterTester(c)) - case "RegisterVecShift" => chiselMainTest(args, () => Module(new RegisterVecShift))(c => new RegisterVecShiftTester(c)) - case "ModuleVec" => chiselMainTest(args, () => Module(new ModuleVec(2)))(c => new ModuleVecTester(c)) - case "ModuleWire" => chiselMainTest(args, () => Module(new ModuleWire))(c => new ModuleWireTester(c)) - case "BundleWire" => chiselMainTest(args, () => Module(new BundleWire))(c => new BundleWireTester(c)) - - case "Stack" => chiselMainTest(args, () => Module(new Stack(16)))(c => new StackTester(c)) - case "GCD" => chiselMainTest(args, () => Module(new GCD))(c => new GCDTester(c)) - case "Risc" => chiselMainTest(args, () => Module(new Risc))(c => new RiscTester(c)) - case "Rom" => chiselMainTest(args, () => Module(new Rom))(c => new RomTester(c)) - case "Outer" => chiselMainTest(args, () => Module(new Outer))(c => new OuterTester(c)) - case "ComplexAssign" => chiselMainTest(args, () => Module(new ComplexAssign(10)))(c => new ComplexAssignTester(c)) - case "UIntOps" => chiselMainTest(args, () => Module(new UIntOps))(c => new UIntOpsTester(c)) - case "SIntOps" => chiselMainTest(args, () => Module(new SIntOps))(c => new SIntOpsTester(c)) - case "BitsOps" => chiselMainTest(args, () => Module(new BitsOps))(c => new BitsOpsTester(c)) - case "DirChange" => chiselMainTest(args, () => Module(new DirChange))(c => new DirChangeTester(c)) - case "VendingMachine" => chiselMainTest(args, () => Module(new VendingMachine))(c => new VendingMachineTester(c)) - case "Pads" => chiselMainTest(args, () => Module(new Pads))(c => new PadsTester(c)) - } - } -} |
