summaryrefslogtreecommitdiff
path: root/src/test/scala/ChiselTests/VecShiftRegister.scala
diff options
context:
space:
mode:
authorHenry Cook2015-08-12 19:32:43 -0700
committerHenry Cook2015-08-12 19:32:57 -0700
commit85d7403f9bf7bc2b3520f924736c237f21f70ebd (patch)
tree64560f779063a419395a2fb8a31ea52c52af4404 /src/test/scala/ChiselTests/VecShiftRegister.scala
parent7e69966362b1dbd9835695250494857f3a3767c8 (diff)
being to convert tests to scala-test; tests compile and run
Diffstat (limited to 'src/test/scala/ChiselTests/VecShiftRegister.scala')
-rw-r--r--src/test/scala/ChiselTests/VecShiftRegister.scala29
1 files changed, 0 insertions, 29 deletions
diff --git a/src/test/scala/ChiselTests/VecShiftRegister.scala b/src/test/scala/ChiselTests/VecShiftRegister.scala
deleted file mode 100644
index ffcfb7a2..00000000
--- a/src/test/scala/ChiselTests/VecShiftRegister.scala
+++ /dev/null
@@ -1,29 +0,0 @@
-package ChiselTests
-import Chisel._
-import Chisel.testers._
-
-class VecShiftRegister extends Module {
- val io = new Bundle {
- val ins = Vec(UInt(INPUT, 4), 4)
- val load = Bool(INPUT)
- val shift = Bool(INPUT)
- val out = UInt(OUTPUT, 4)
- }
- val delays = Reg(Vec(UInt(width = 4), 4))
- when (io.load) {
- delays(0) := io.ins(0)
- delays(1) := io.ins(1)
- delays(2) := io.ins(2)
- delays(3) := io.ins(3)
- } .elsewhen(io.shift) {
- delays(0) := io.ins(0)
- delays(1) := delays(0)
- delays(2) := delays(1)
- delays(3) := delays(2)
- }
- io.out := delays(3)
-}
-
-
-class VecShiftRegisterTester(c: VecShiftRegister) extends Tester(c) {
-}